The present invention relates to an impedance matching circuit in a semiconductor memory device; more particularly, to ZQ calibration performed by the impedance matching circuit.
As an operation speed of electrical products increases, a swing width of signals transmitted between semiconductor memory devices inside the electrical products decreases to minimize a delay time taken to transmit the signals. However, as the swing width decreases, signal transmission is more affected by external noises and signal reflection in an interface terminal would increase by impedance mismatching.
The impedance mismatching is caused by variation of a manufacture process, a supply voltage and an operation temperature (PVT). The impedance mismatching makes it hard to transmit data at a high speed. Because a signal outputted from a semiconductor memory device may be distorted by the impedance mismatching, malfunctions such as a set up/hold fail and misjudgment of the signal level could be caused in a corresponding semiconductor memory device receiving the distorted signal.
A semiconductor memory device includes an input circuit for receiving external signals through an input pad and an output circuit for outputting internal signals through an output pad. Particularly, a semiconductor memory device which is required to operate at a high speed includes an impedance matching circuit for matching interface impedance with a corresponding semiconductor memory device in order to prevent the above malfunctions.
Generally, in a semiconductor memory device transmitting a signal, a source termination is performed by an output circuit. In a semiconductor memory device receiving a signal, a parallel termination is performed by a termination circuit parallelly connected to the input circuit.
ZQ calibration is a process for generating pull-up and pull-down calibration codes which change as conditions of PVT change. A resistance value of input and output circuit is calibrated by using the codes. The ZQ calibration performed in the impedance matching circuit is described below.
FIG. 1 is a block diagram illustrating a conventional impedance matching circuit. The impedance matching circuit includes a first pull-up resistor PU1, a second pull-up resistor PU2, a pull-down resistor PD, a reference voltage generator 103, comparators 104 and 107 and counters 105 and 108.
When the first pull-up resistor PU1 is coupled to an external resistor 101 through a pad ZQ, a voltage is generated at a first node 102. The external resistor 101 generally has resistance of 240Ω. The comparator 104 compares the voltage at the first node 102 with a reference voltage VREF outputted from the reference voltage generator 103, to thereby generate an up/down signal UP/DOWN. The reference voltage VREF is generally set to a half of supply voltage VDDQ/2.
The counter 105 receives the up/down signal UP/DOWN to thereby generate a binary code PCODE<0:N>. The binary code PCODE<0:N> turns on/off MOS transistors coupled in parallel in the first pull-up resistor PU1, to thereby calibrate resistance. The calibrated resistance of the first pull-up resistor PU1 has an effect on the voltage at the first node 102. Above operations are repeated. That is, calibration, i.e., pull-up calibration, is performed in the first pull-up resistor PU1 in order for the resistance of the first pull-up resistor PU1 to become identical to the resistance of the external resistor 101.
The binary code PCODE<0:N> is also inputted into the second pull-up resistor PU2 and determines resistance of the second pull-up resistor PU2. Similarly with the pull-up calibration, a pull-down calibration is performed. A voltage at a second node 106 becomes identical to the reference voltage VREF by a binary code NCODE<0:N> generated by the comparator 107 and the counter 108. The pull-down calibration is performed in order for resistance of the pull-down resistor PD to become identical to the resistance of the second pull-up resistor PU2.
The ZQ calibration includes the pull-up calibration and the pull-down calibration. The binary codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration are inputted to input or output circuits and calibrate their resistance to an external resistance.
FIG. 2 is a graph depicting a voltage level changed by the calibration. As a predetermined period elapses, the voltages at the first and second node 102 and 106 converge on the level of the reference voltage.
As described above, the conventional impedance matching circuit performs the pull-up calibration in order for the external resistor 101 to have identical resistance with the first pull-up resistor PU1, and performs the pull-down calibration in order for the second pull-up resistor PU2 to have identical resistance with the pull-down resistor PD.
Accordingly, on condition that the external resistor 101 is connected through the pad ZQ, it is possible that the impedance matching circuit performs the calibration. After connecting the external resistor 101 with a semiconductor memory device packaged in advance, a test for checking the calibration operation can be performed. In a semiconductor memory device processes such as a wafer process, prior to a packaging process, the calibration operation cannot be tested.